Online Interactive Session on Solvnet Helpdesk by Synopsys Team- Reg.

The Session will cover the following topic's:

• How to register on SolvNet.
• Locating the SITE ID on SolvNet.
• How to raise a support ticket on SolvNet for various issues (e.g., tool download, tool features related, design support related, etc.)
• Accessing documentation for any Synopsys product on SolvNet.
• Locating tool binaries, SCL, and other related resources.
• Accessing SAED PDKs.
• Finding training content (including self-paced and university curriculum modules)

Technical (Online) Session on Open-source tools for improved debugging and modularity with Chisel by Dr. H. Peter Hofstee (IBM)

Abstract of the Talk: This Talk will introduce a set of open-source tools and a new standard for typed streams to deliver a better experience for designing with the Chisel high-level design language. Currently, while Chisel allows designs to be specified in a higher-level language, debugging a design still happens at a very low level. We introduce several new tools compatible with Chisel to address this.

• The Tywaves waveform viewer, built on the "surfer" waveform viewer platform, enables waveforms that preserve and properly visualize the Chisel data structures and types. The ChiselWatt OpenPOWER processor is used as an example design.
• We also introduce a tool (ChiselTrace) that allows for improved traceback from selected signals that can be used to more efficiently discover the causes of an erroneous signal value.
• Next, we introduce the Tydi framework, that provides typed streaming interfaces that can be used to improve modularity and reusability of designs in Chisel (Tydi-Chisel) as well as other languages. At the end we summarize on how this collection of tools can simplify hardware design, and we discuss how we plan to take this work forward.

Two- Days Technical (Online) Session on Low-Power RTL Synthesis Flow using Cadence EDA Tools

Day 1

Session-1: Joules Power Calculator (2:00 PM - 3:30 PM)

• Introduction to Cadence Joules RTL Power Solution
• Estimating the Power and Joules Power Reduction Techniques
• Genus-Joules Integration

Session-2: Low-Power Specification Format (3:45 PM - 5:30 PM)

• Low-power concepts and strategies
• Implement a power switch
• Debugging Design Scenarios

Two- Days Technical (Online) Session on Low-Power RTL Synthesis Flow using Cadence EDA Tools

Day 2

Session-3: Genus Low-Power Synthesis Flow (2:00 PM - 3:30 PM)

• Low-Power Synthesis Flow
• Power Reduction
• Low-Power Methodologies: MSV, PSO, and DVFS

Session-4: Low-Power Synthesis Flow with Genus Stylus (3:45 PM - 5:30 PM)

• Troubleshooting Low-Power Design
• Checking a Low-Power Design with Conformal Software
• Genus-Joules Integration

Technical (Online) Session on Post-Silicon Validation, Characterization, Testing, and Packaging Services by Tessolve for C2S Participants

The Session will cover the following topics:

• Overview of Tessolve and Post Si Support Flow.
• Capabilities in Test Engineering
• Bench Characterization Capabilities
• Overview of Product Engineering
• Introduction to Qualification
• Expertise in PCB Engineering
• Capabilities in Packaging
• Q & A and support for C2S participants.

Online Webinar Series Engineering Tomorrow: Launch your Semiconductor Career with Siemens EDA

The Session will cover the following topics:

• To build awareness around Electronic Design Automation (EDA) technologies and highlight how Siemens EDA's industry-leading products are shaping the future of semiconductor and electronic design

• A foundational element of design verification involves establishing correctness by construction, which will be explored through the Design Linting process. This will be succeeded by a discussion on the imperative for robust clock domain and reset domain crossings implementation and verification.
• The session will then transition to an exploration of Formal Verification technologies. These are emerging as a potent solution, facilitating early design analysis independent of testbench development. We will elucidate how formal verification contributes to mathematically proven design correctness, exhaustive verification coverage, and the early identification of corner-case scenarios.

Technical Online Session on IC Packaging: Trends & Challenges by Cadence Team

The Session details will be shared shortly

Beyond VLSI -Unveiling the Critical Role of PCB and IC Package Design in Modern Electronics

This Session provides a foundational understanding of IC Packaging and PCB Design.

• We will explore the electrical complexities of PCB & IC Package design in the context of high-performance systems and challenges involved around them. Participants will gain insights into leveraging PCB design and analysis tools, learning how to navigate manufacturability challenges and apply industry-leading best practices. The session will also showcase how sophisticated design platforms, such as Xpedition, can revolutionize design flow management.
• Furthermore, we'll explore the fundamental principles of Signal and Power Integrity in the context of both PCB and IC Packaging, demonstrating how simulation and analysis tools are indispensable for optimizing designs to achieve peak functional and performance efficiency.

Technical (Online) Session on Design. Verify. Innovate: Discover the Power of Analog Design

This Session covers a high-level understanding on Analog IP design flow right from designing transistor level schematics, enabling accurate circuit behaviour analysis, verification, and optimization before fabrication using industry standard EDA tools.

Technical (Online) Session on Fusion Compiler Session by Synopsys Team

The Session will cover the following topics:

• Introduction to VLSI
• VLSI Design flow & Inputs used
• Fusion Compiler Synthesis Flow
• DFT - Design for Test
• Fusion Compiler P&R Flow
• Optimization technologies that deliver the best PPA / QoR
• Signoff checks and Tools (Formality, ICV, STARRC, PT)
• Demo